Controller and operation method thereof

ABSTRACT

A controller includes a memory suitable for storing first data read from first memory blocks of a first super memory block included in a memory device; a rearranging unit suitable for rearranging the first data stored in the memory based on sequence-information of the first data stored in the memory; and a processor suitable for controlling the memory device to write the rearranged first data in a second super memory block of the memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/655,206 filed on Jul. 20, 2017, which claims benefits of priority ofKorean Patent Application No. 10-2016-0184095 filed on Dec. 30, 2016.The disclosure of each of the foregoing application is incorporatedherein by reference in its entirety.

BACKGROUND 1. Field

Various embodiments of the present invention relate to a controller and,more particularly, a controller and operation method thereof.

2. Description of the Related Art

The computer environment paradigm has shifted to ubiquitous computingsystems that can be used anytime and anywhere. As a result, use ofportable electronic devices such as mobile phones, digital cameras, andnotebook computers continues to increase rapidly. These portableelectronic devices generally use a memory system having one or moresemiconductor memory devices also referred to as data storage devices.The data storage device may be used as the main memory device or anauxiliary memory device of a portable electronic device.

Semiconductor memory devices provide excellent stability, durability,high information access speed, and low power consumption, since theyhave no moving parts. Examples of data storage devices include universalserial bus (USB) memory devices, memory cards having various interfaces,and solid state drives (SSD).

SUMMARY

Various embodiments are directed to a controller capable of preventingperformance degradation of a read operation to sequential data evenafter a plurality of copy operations are performed for the sequentialdata, and an operation method thereof.

In accordance with an embodiment of the present invention, a controllermay include: a memory suitable for storing first data read from firstmemory blocks of a first super memory block included in a memory device;a rearranging unit suitable for rearranging the first data stored in thememory based on sequence-information of the first data stored in thememory; and a processor suitable for controlling the memory device towrite the rearranged first data in a second super memory block of thememory device.

Preferably, the rearranging unit may rearrange the first datasequentially based on sequence-information.

Preferably, the rearranging unit may rearrange the first data when asize of the first data is equal to or larger than a first threshold.

Preferably, the first threshold may be equal to or larger than a storagecapacity of one or more pages of the first memory blocks included in thefirst super memory block.

Preferably, the sequence-information may include information of logicblock addresses.

Preferably, the first data may be sequential data.

Preferably, the processor may copy the first data from the first supermemory block to the second super memory block according to the order ofthe sequence-information of the first data.

Preferably, the first threshold may be equal to or smaller than apredetermined storage capacity of the first super memory block.

Preferably, the rearranging unit may rearrange the first data stored inthe memory when the processor copies the first data from the first supermemory block to the second super memory block via the memory.

Preferably, the processor may copy the first data during a garbagecollection operation.

In accordance with an embodiment of the present invention, a method foroperating a controller includes: storing first data read from firstmemory blocks of a first super memory block included in a memory device;rearranging the first data stored in the memory based onsequence-information of the first data stored in the memory; andcontrolling the memory device to write the rearranged first data in asecond super memory block of the memory device.

Preferably, the rearranging may rearrange the first data sequentiallybased on sequence-information.

Preferably, the rearranging may rearrange the first data when a size offirst data is equal to or larger than a first threshold.

Preferably, the first threshold may be equal to or larger than a storagecapacity of one or more pages of the first memory blocks included in thefirst super memory block.

Preferably, the sequence-information may include information of logicblock addresses.

Preferably, the first data may be sequential data.

Preferably, the processor may copy the first data from the first supermemory block to the second super memory block according to the order ofthe sequence-information of the first data.

Preferably, wherein the first threshold may be equal to or smaller thana predetermined storage capacity of the first super memory block.

Preferably, the rearranging may rearrange the first data stored in thememory during a copy operation of copying the first data from the firstsuper memory block to the second super memory block via the memory.

Preferably, the copy operation may be performed during a garbagecollection operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a data processing system including amemory system according to an embodiment.

FIG. 2 is a diagram illustrating a memory device according to anembodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a memory block in a memorydevice according to an embodiment of the present invention.

FIG. 4 is a diagram schematically illustrating an aspect of the memorydevice shown in FIG. 2 according to an embodiment of the presentinvention.

FIG. 5 is a diagram illustrating a memory system shown in FIG. 1.

FIG. 6 is a diagram illustrating a comparative example of moving datafrom a memory of a controller to a super memory block withoutrearranging the data.

FIGS. 7 to 9 are diagrams illustrating an operation of a controlleraccording to an embodiment of the present invention.

FIGS. 10 to 18 are diagrams schematically illustrating the otherembodiments of a data process system including a memory system accordingto an embodiment of the present invention.

DETAILED DESCRIPTION

Various embodiments will be described below in more detail withreference to the accompanying drawings. The present invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure is thorough and complete.Throughout the disclosure, like reference numerals refer to like partsthroughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When an element is referred to as beingconnected or coupled to another element, it should be understood thatthe former can be directly connected or coupled to the latter, orelectrically connected or coupled to the latter via an interveningelement therebetween. Furthermore, when it is described that one“comprises” (or “includes”) or “has” some elements, it should beunderstood that it may comprise (or include) or have other elements aswell as those elements if there is no specific limitation. The terms ofsingular form may include plural forms unless stated otherwise.

FIG. 1 is a block diagram illustrating a data processing systemincluding a memory system according to an embodiment.

Referring to FIG. 1, a data processing system 100 may include a host 102and a memory system 110.

The host 102 may include, for example, a portable electronic device suchas a mobile phone, an MP3 player and a laptop computer or an electronicdevice such as a desktop computer, a game player, a TV, a projector andthe like.

The host 102 may include one or more operating system, and the operationsystem may control and manage operation and performance of the host 102,and provide inter-operation between the host 102 and user using the dataprocessing system 100 or the memory system 110. The operating system maysupport operation and performance corresponding to purpose of use. Forexample, depending on the mobility of the host, it may be classifiedinto a general operating system and a mobile operating system. And,depending on the environment of user, the general operating system maybe classified into a personal operating system and an enterpriseoperating system. For example, the personal operating system may provideservice for general users and include window and chrome and so on. Theenterprise operating system may be specialized system to provide highquality, and include windows server, linux and unix and so on. And themobile operating system may be specialized system to provide a systempower saving function and a mobile service to users and include android,iOS, windows mobile and so on. The host 102 may include a plurality ofthe operating systems, and perform an operating system for operationwith the memory system 110 corresponding to request of user.

The memory system 110 may operate in response to a request from the host102, and in particular, store data to be accessed by the host 102. Thememory system 110 may be used as a main memory system or an auxiliarymemory system of the host 102. The memory system 110 may be implementedwith any one of various types of storage devices, which may beelectrically coupled with the host 102, according to a protocol of ahost interface. Examples of suitable storage devices include a solidstate drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), areduced size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card, amini-SD and a micro-SD, a universal serial bus (USB) storage device, auniversal flash storage (UFS) device, a compact flash (CF) card, a smartmedia (SM) card, a memory stick, and the like.

The storage devices for the memory system 110 may be implemented with avolatile memory device such as a dynamic random access memory (DRAM) anda static random access memory (SRAM) or a nonvolatile memory device suchas a read only memory (ROM), a mask ROM (MROM), a programmable ROM(PROM), an erasable programmable ROM (EPROM), an electrically erasableprogrammable ROM (EEPROM), a ferroelectric random access memory (FRAM),a phase change RAM (PRAM), a magnetic RAM (MRAM) and a resistive RAM(RRAM).

The memory system 110 may include a memory device 150 which stores datato be accessed by the host 102, and a controller 130 which may controlstorage of data in the memory device 150.

The controller 130 and the memory device 150 may be integrated into onesemiconductor device. For instance, the controller 130 and the memorydevice 150 may be integrated into one semiconductor device such as asolid state drive (SSD). When the memory system 110 is used as a SSD,the operation speed of the host 102 that is electrically coupled withthe memory system 110 may be significantly increased.

The controller 130 and the memory device 150 may be integrated into onesemiconductor device and be configured as a memory card. The controller130 and the memory card 150 may be integrated into one semiconductordevice and be configured as a memory card such as a Personal ComputerMemory Card International Association (PCMCIA) card, a compact flash(CF) card, a smart media (SM) card (SMC), a memory stick, a multimediacard (MMC), an RS-MMC and a micro-MMC, a secure digital (SD) card, amini-SD, a micro-SD and an SDHC, and a universal flash storage (UFS)device.

The memory system 110 may be configured as part of a computer, anultra-mobile PC (UMPC), a workstation, a net-book, a personal digitalassistant (PDA), a portable computer, a web tablet, a tablet computer, awireless phone, a mobile phone, a smart phone, an e-book, a portablemultimedia player (PMP), a portable game player, a navigation device, ablack box, a digital camera, a digital multimedia broadcasting (DMB)player, a three-dimensional (3D) television, a smart television, adigital audio recorder, a digital audio player, a digital picturerecorder, a digital picture player, a digital video recorder, a digitalvideo player, a storage configuring a data center, a device capable oftransmitting and receiving information under a wireless environment, oneof various electronic devices configuring a home network, one of variouselectronic devices configuring a computer network, one of variouselectronic devices configuring a telematics network, an RFI© device, orone of various component elements configuring a computing system.

The memory device 150 of the memory system 110 may retain stored datawhen power supply is interrupted, for example, the memory device maystore the data provided from the host 102 during a write operation, andprovide stored data to the host 102 during a read operation. The memorydevice 150 may include a plurality of memory blocks 152, 154 and 156.Each of the memory blocks 152, 154 and 156 may include a plurality ofpages. Each of the pages may include a plurality of memory cells towhich a plurality of word lines (WL) are electrically coupled. Thememory device 150 may be a nonvolatile memory device, for example, aflash memory. The flash memory may have a three-dimensional (3D) stackstructure. The memory device may have any other suitable structure.

The controller 130 may control overall operations of the memory device150, such as read, write, program and erase operations. For example, thecontroller 130 of the memory system 110 may control the memory device150 in response to a request from the host 102. The controller 130 mayprovide the data read from the memory device 150, to the host 102,and/or may store the data provided from the host 102 into the memorydevice 150.

The controller 130 may include a host interface unit 132, a processor134, an error correction code (ECC) unit 138, a power management unit140, a NAND flash controller 142, a memory 144 and a rearranging unit146.

The host interface unit 132 may process commands and data provided fromthe host 102, and may communicate with the host 102 through at least oneof various interface protocols such as universal serial bus (USB),multimedia card (MMC), peripheral component interconnect-express(PCI-E), serial attached SCSI (SAS), serial advanced technologyattachment (SATA), parallel advanced technology attachment (PATA), smallcomputer system interface (SCSI), enhanced small disk interface (ESDI),and integrated drive electronics (IDE).

The ECC unit 138 may detect and correct errors in the data read from thememory device 150 during the read operation. The ECC unit 138 may notcorrect error bits when the number of the error bits is greater than orequal to a threshold number of correctable error bits, and may output anerror correction fail signal indicating failure in correcting the errorbits.

The ECC unit 138 may perform an error correction operation based on acoded modulation such as a low density parity check (LDDC) code, aBose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS)code, a convolution code, a recursive systematic code (RSC), atrellis-coded modulation (TCM), a Block coded modulation (BCM), and soon. The ECC unit 138 may include all circuits, systems or devices forthe error correction operation.

The PMU 140 may provide and manage power for the controller 130, thatis, power for the component elements included in the controller 130.

The NFC 142 may serve as a memory interface between the controller 130and the memory device 150 to allow the controller 130 to control thememory device 150 in response to a request from the host 102. The NFC142 may generate control signals for the memory device 150 and processdata under the control of the processor 134 when the memory device 150is a flash memory and, in particular, when the memory device 150 is aNAND flash memory.

The memory 144 may serve as a working memory of the memory system 110and the controller 130, and store data for driving the memory system 110and the controller 130. The controller 130 may control the memory device150 in response to a request from the host 102. For example, thecontroller 130 may provide the data read from the memory device 150 tothe host 102 and store the data provided from the host 102 in the memorydevice 150. When the controller 130 controls the operations of thememory device 150, the memory 144 may store data used by the controller130 and the memory device 150 for such operations as read, write,program and erase operations.

The memory 144 may be implemented with volatile memory. The memory 144may be implemented with a static random access memory (SRAM) or adynamic random access memory (DRAM). As described above, the memory 144may store data used by the host 102 and the memory device 150 for theread and write operations. To store the data, the memory 144 may includea program memory, a data memory, a write buffer, a read buffer, a mapbuffer, and so forth.

When a size of data stored in the memory 144 exceeds a firstpredetermined threshold, the rearranging unit 146 may rearrange databased on sequence-information of data. The sequence-information mayinclude information for a logical block address of data.

The processor 134 may control general operations of the memory system110, and a write operation or a read operation for the memory device150, in response to a write request or a read request from the host 102.The processor 134 may drive firmware, which is referred to as a flashtranslation layer (FTL), to control the general operations of the memorysystem 110. The processor 134 may be implemented with a microprocessoror a central processing unit (CPU).

A management unit (not shown) may be included in the processor 134, andmay perform bad block management of the memory device 150. Themanagement unit may find bad memory blocks included in the memory device150, which are in unsatisfactory condition for further use, and performbad block management on the bad memory blocks. When the memory device150 is a flash memory, for example, a NAND flash memory, a programfailure may occur during the write operation, for example, during theprogram operation, due to characteristics of a NAND logic function.During the bad block management, the data of the program-failed memoryblock or the bad memory block may be programmed into a new memory block.Also, the bad blocks due to the program fail seriously deteriorates theutilization efficiency of the memory device 150 having a 3D stackstructure and the reliability of the memory system 100, and thusreliable bad block management is required.

FIG. 2 is a schematic diagram illustrating the memory device 150 shownin FIG. 1.

Referring to FIG. 2, the memory device 150 may include a plurality ofmemory blocks, for example, zeroth to (N−1)^(th) blocks 210 to 240. Eachof the plurality of memory blocks 210 to 240 may include a plurality ofpages, for example, 2^(M) number of pages (2^(M) PAGES). Each of theplurality of pages may include a plurality of memory cells. A pluralityof word lines may be electrically coupled to the memory cells.

The memory device 150 may include a plurality of memory blocks, assingle level cell (SLC) memory blocks and multi-level cell (MLC) memoryblocks, according to the number of bits which may be stored or expressedin each memory cell. The SLC memory block may include a plurality ofpages which are implemented with memory cells each capable of storing1-bit data. The MLC memory block may include a plurality of pages whichare implemented with memory cells each capable of storing multi-bitdata, for example, two or more-bit data. An MLC memory block including aplurality of pages which are implemented with memory cells that are eachcapable of storing 3-bit data may be defined as a triple level cell(TLC) memory block.

Each of the plurality of memory blocks 210 to 240 may store the dataprovided from the host device 102 during a write operation, and mayprovide stored data to the host 102 during a read operation.

FIG. 3 is a circuit diagram illustrating one of the plurality of memoryblocks 152 to 156 shown in FIG. 1.

Referring to FIG. 3, the memory block 152 of the memory device 150 mayinclude a plurality of cell strings 340 which are electrically coupledto bit lines BL0 to BLm−1, respectively. The cell string 340 of eachcolumn may include at least one drain select transistor DST and at leastone source select transistor SST. A plurality of memory cells or aplurality of memory cell transistors MC0 to MCn−1 may be electricallycoupled in series between the select transistors DST and SST. Therespective memory cells MC0 to MCn−1 may be configured by single levelcells (SLC) each of which may store 1 bit of information, or bymulti-level cells (MLC) each of which may store data information of aplurality of bits. The strings 340 may be electrically coupled to thecorresponding bit lines BL0 to BLm−1, respectively. For reference, inFIG. 3, ‘DSL’ denotes a drain select line, ‘SSL’ denotes a source selectline, and ‘CSL’ denotes a common source line.

While FIG. 3 only shows, as an example, the memory block 152 which isconfigured by NAND flash memory cells, it is to be noted that the memoryblock 152 of the memory device 150 according to the embodiment is notlimited to NAND flash memory and may be realized by NOR flash memory,hybrid flash memory in which at least two kinds of memory cells arecombined, or one-NAND flash memory in which a controller is built in amemory chip. The operational characteristics of a semiconductor devicemay be applied to not only a flash memory device in which a chargestoring layer is configured by conductive floating gates but also acharge trap flash (CTF) in which a charge storing layer is configured bya dielectric layer.

A voltage supply block 310 of the memory device 150 may provide wordline voltages, for example, a program voltage, a read voltage and a passvoltage, to be supplied to respective word lines according to anoperation mode and voltages to be supplied to bulks, for example, wellregions in which the memory cells are formed. The voltage supply block310 may perform a voltage generating operation under the control of acontrol circuit (not shown). The voltage supply block 310 may generate aplurality of variable read voltages to generate a plurality of readdata, select one of the memory blocks or sectors of a memory cell arrayunder the control of the control circuit, select one of the word linesof the selected memory block, and provide the word line voltages to theselected word line and unselected word lines.

A read/write circuit 320 of the memory device 150 may be controlled bythe control circuit, and may serve as a sense amplifier or a writedriver according to an operation mode. During a verification/normal readoperation, the read/write circuit 320 may serve as a sense amplifier forreading data from the memory cell array. Also, during a programoperation, the read/write circuit 320 may serve as a write driver whichdrives bit lines according to data to be stored in the memory cellarray. The read/write circuit 320 may receive data to be written in thememory cell array, from a buffer (not shown), during the programoperation, and may drive the bit lines according to the inputted data.For example, the read/write circuit 320 may include a plurality of pagebuffers 322, 324 and 326 respectively corresponding to columns (or bitlines) or pairs of columns (or pairs of bit lines), and a plurality oflatches (not shown) may be included in each of the page buffers 322, 324and 326.

FIG. 4 is a block diagram illustrating an example of the plurality ofmemory blocks 152 to 156 of the memory device 150 shown in FIG. 1.

Referring to FIG. 4, the memory device 150 may include a plurality ofmemory blocks BLK0 to BLKN−1, and each of the memory blocks BLK0 toBLKN−1 may be realized in a three-dimensional (3D) structure or avertical structure. Each memory block BLK0 to BLKN−1 may include astructure which extends in first to third directions, for example, anx-axis direction, a y-axis direction and a z-axis direction.

The respective memory blocks BLK0 to BLKN−1 may include a plurality ofNAND strings NS which extend in the second direction. The plurality ofNAND strings NS may be provided in the first direction and/or the thirddirections. Each NAND string NS may be electrically coupled to a bitline BL, at least one source select line SSL, at least one ground selectline GSL, a plurality of word lines WL, at least one dummy word lineDWL, and a common source line CSL. The respective memory blocks BLK0 toBLKN−1 may be electrically coupled to a plurality of bit lines BL, aplurality of source select lines SSL, a plurality of ground select linesGSL, a plurality of word lines WL, a plurality of dummy word lines DWL,and a plurality of common source lines CSL.

FIG. 5 is a diagram illustrating the memory system 110.

The processor 134 may manage a super memory block. The super memoryblock may include a plurality of memory blocks, which the processor 134can control at a time. Referring to FIG. 5, the processor 134 may managesuper memory blocks 521 and 522 respectively grouped by one or morememory blocks BLOCK 0 to BLOCK 7 included in respective memory dies 511to 514 of the memory device 150. FIG. 5 illustrates that the processor134 manage memory blocks BLOCK 0 to 3 through a first super memory block521, and manage memory blocks BLOCK 4 to 7 through a second super memoryblock 522.

The processor 134 may control the memory blocks BLOCK 0 to 7 of thesuper memory blocks 521 and 522 through an interleaving scheme such asthe channel interleaving, the memory die interleaving, the memory chipinterleaving, a way interleaving, and so on. The processor 134 maysequentially control the memory blocks BLOCK 0 to 7 of the super memoryblocks 521 and 522 on a page basis through the interleaving scheme.

Referring to FIG. 5, when the processor 134 receives from the host 102 awrite request of sequential data LBA 0 to 11, logical block addresses ofwhich are sequential, the processor 134 may control the memory device150 to write the sequential data LBA 0 to respectively into first pagesof the memory blocks BLOCK 0 to 3 in a sequential manner.

Likewise, the processor 134 may control the memory device 150 to writethe sequential data LBA 4 to 11 respectively into second pages and thirdpages of the memory blocks BLOCK 0 to 3 in sequential manner. That is,the processor 134 may control the memory device 150 to write thesequential data LBA 0 to 11 respectively into the first super memoryblock 521 through the interleaving scheme.

Referring to FIG. 5, when the processor 134 receive from the host 102 aread request of sequential data LBA 0 to 11 stored in the first supermemory block 521, the processor 134 may control the memory device 150 toread the sequential data LBA 0 to 3 respectively from the first pages ofthe memory blocks BLOCK 0 to 3 in sequential manner.

Likewise, the processor 134 may control the memory device 150 to readthe sequential data LBA 4 to 11 respectively from the second pages orthird pages of the memory blocks BLOCK 0 to 3 in sequential manner. Thatis, the processor 134 may control the memory device 150 to read thesequential data LBA 0 to 11 respectively from the first super memoryblock 521 through the interleaving scheme.

FIG. 6 is a diagram illustrating a comparative example of moving datafrom a memory 6144 of a controller 6130 to a super memory block 6522without rearranging the data.

Although a processor of the controller 6130 controls a memory device6150 through the interleaving scheme, sequential data LBA 0 to 11 may berandomly read from a first super memory block 6521 in the memory device6150 and the randomly read sequential data LBA 0 to 11 may be stored inthe memory 6144 in random manner. This is because times required to readdata from respective memory blocks BLOCK 0 to 7 of the first supermemory block 6521 are different from one another.

Referring to FIG. 6, when the processor 6134 of the controller 6130controls the memory device 6150 to write the sequential data LBA 0 to11, which are randomly stored in the memory 6144 of the controller 6130through the interleaving scheme, into a second memory block 6522 duringa copy operation of copying the sequential data LBA 0 to 11 from thefirst super memory block 6521 to the second super memory block 6522through the memory 6144, the sequential data LBA 0 to 11 may be randomlystored in the second memory block 6522. That is, when the processorcopies the sequential data LBA 0 to 11 stored in the first super memoryblock 6521 into the second super memory block 6522 during a garbagecollection operation for example, the sequential data LBA 0 to 11 mayeventually become random while being stored in the second super memoryblock 6522. Accordingly, it may take longer time to read out therandomized sequential data LBA 0 to 11 from the second super memoryblock 6522, which decreases efficiency of the reading operation to theoriginally sequential data LBA 0 to 11.

In accordance with an embodiment of the present invention, thecontroller 130 may include the rearranging unit 146 suitable forrearranging the order of the randomized sequential data. The controller130 may solve the problem which takes longer time to read out therandomized sequential data using the rearranging unit 146. Therearranging unit 146 may be implemented by using a processor, acomputer, or a firm-ware type processing unit.

When the size of the sequential data LBA 0 to 11 stored in the memory144 exceeds a first threshold, the rearranging unit 146 may rearrangethe sequential data LBA 0 to 11 based on the sequence-information (i.e.,logic block addresses) of the sequential data LBA 0 to 11. The firstthreshold may be equal to or larger than a storage capacity of one ormore pages of the super memory blocks 521 and 522. For example, when thestorage capacity of each page of the memory blocks BLOCK 0 to 7 in thesuper memory blocks 521 and 522 is 16 KB, the first threshold may beequal to or greater than 16 KB. As the first threshold becomes larger,the rearranging unit 146 may rearrange more data.

FIGS. 7 to 9 are diagrams illustrating an operation of the controller130 according to an embodiment of the present invention.

In accordance with an embodiment of the present invention, the processor134 may copy the sequential data LBA 0 to 11, which are stored in thefirst super memory block 521, into the second super memory block 522through the memory 144. First, the processor 134 may store thesequential data in the memory 144. However, the sequential data maybecome random while being stored in the memory 144. The rearranging unit146 may rearrange the randomly stored data LBA 0 to 11 in the memory144.

Hereinafter, it is assumed that each size of the sequential data LBA 0to 11 is equal to storage capacity of each page in the memory blocksBLOCK 0 to 7. Further, it is assumed that the first threshold is storagecapacity of 5 pages. For example, when the storage capacity of each pagein the memory block BLOCK 0 to 7 is 16 KB, the each size of thesequential data LBA 0 to 11 may be 16 KB and the first threshold may be80 KB.

As illustrated in FIG. 7, when the sequential data LBA 0 to 5 are readfrom the first super memory block 521 and then stored in the memory 144during the copy operation of copying in a sequential manner thesequential data LBA 0 to 11 from the first super memory block 521 to thesecond super memory block 522 via the memory 144, the size of thesequential data LBA 0 to 5 may be 96 KB and thus exceed the firstthreshold of 80 KB. Therefore, the rearranging unit 146 may rearrangethe sequential data LBA 0 to 5, which are now stored in the memory 144,based on the logic block addresses of the sequential data LBA 0 to 5.When the sequential data LBA 0 to 5 which are stored in the memory arerearranged, the processor 134 may store into first pages of the secondsuper memory block 522 four sequential data LBA 0 to 3 among thesequential data LBA 0 to 5 rearranged in the memory 144.

As illustrated in FIG. 8, during the copy operation of copying in asequential manner the sequential data LBA 0 to 11 from the first supermemory block 521 to the second super memory block 522 via the memory144, four sequential data LBA 6 to 9 may be further stored in the memory144 while two sequential data LBA 4 and 5 still remain stored in thememory 144. Therefore, the size, which is 96 KB, of the six sequentialdata LBA 4 to 9 may exceed the first threshold, which is 80 KB.

Accordingly, rearranging unit 146 may rearrange the six sequential dataLBA 4 to 9 based on logic block addresses of the sequential data LBA 4to 9 stored in the memory 144. When the sequential data LBA 4 to 9stored in the memory 144 are rearranged, the processor 134 may storeinto second pages of the second super memory block 522 four sequentialdata LBA 4 to 7 among the sequential data LBA 4 to 9 rearranged in thememory 144.

As illustrated in FIG. 9, during the copy operation of copying insequential manner the sequential data LBA 0 to 11 from the first supermemory block 521 to the second super memory block 522 via the memory144, two sequential data LBA 10 to 11 may be further stored in thememory 144 while two sequential data LBA 8 and 9 still remain stored inthe memory 144. Therefore, the size, which is 64 KB, of the sequentialdata LBA 8 to 11 stored in the memory 144 may not exceed the firstthreshold, which is 80 KB.

Accordingly, the rearranging unit 146 may not rearrange the sequentialdata LBA 8 to 11 stored in the memory 144. And the processor 134 maystore the sequential data LBA 8 to 11, which are not rearranged in thememory 144, into third pages of the second memory block 522.

In an embodiment, it is possible that the rearranging unit 146rearranges the sequential data LBA 8 to 11 stored in the memory 144despite the first threshold.

In an embodiment of the present invention described above, the memorydevice 150 may write the sequential data into the super memory blockimmediately when the memory device 150 receives the sequential data fromthe processor 134. In an embodiment, the memory device 150 may gatherthe sequential data each time the processor 134 provides partial piecesof all the sequential data until all of the sequential data is providedto the memory device 150, and then the memory device 150 write all ofthe sequential data at once into the second super memory block 522through the one-shot program scheme.

In accordance with an embodiment of the present invention as describedabove, during the copy operation of copying in sequential manner thesequential data LBA 0 to 11 from the first super memory block 521 to thesecond super memory block 522 via the memory 144, the memory system 110may store the sequential data LBA 0 to 11 into the second super memoryblock 522 in a sequential manner. Therefore, despite several copyoperations of copying the sequential data LBA 0 to 11 from the firstsuper memory block 521 to the second super memory block 522 via thememory 144, it may not take longer time to read out the sequential dataLBA 0 to 11 from the second super memory block 522, which preventsefficiency decrease of the reading operation to the sequential data LBA0 to 11.

FIGS. 10 to 18 are diagrams schematically illustrating applicationexamples of the data processing system of FIG. 1.

FIG. 10 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance withthe present embodiment. FIG. 10 schematically illustrates a memory cardto which a memory system in accordance with an embodiment of the presentinvention is applied.

Referring to FIG. 10, the memory card 6000 may include a memorycontroller 6020, a memory device 6030 and a connector 6010.

More specifically, the memory controller 6020 may be connected to thememory device 6030 embodied by a nonvolatile memory, and configured toaccess the memory device 6030. For example, the memory controller 6020may be configured to control read, write, erase and backgroundoperations of the memory device 6030. The memory controller 6020 may beconfigured to provide an interface between the memory device 6030 and ahost, and drive firmware for controlling the memory device 6030. Thatis, the memory controller 6020 may correspond to the controller 130 ofthe memory system 110 described with reference to FIG. 1, and the memorydevice 6030 may correspond to the memory device 150 of the memory system110 described with reference to FIG. 1.

Thus, the memory controller 6020 may include a RAM, a processing unit, ahost interface, a memory interface and an error correction unit.

The memory controller 6020 may communicate with an external device, forexample, the host 102 of FIG. 1 through the connector 6010. For example,as described with reference to FIG. 1, the memory controller 6020 may beconfigured to communicate with an external device through one or more ofvarious communication protocols such as universal serial bus (USB),multimedia card (MMC), embedded MMC (eMMC), peripheral componentinterconnection (PCI), PCI express (PCIe), Advanced TechnologyAttachment (ATA), Serial-ATA, Parallel-ATA, small computer systeminterface (SCSI), enhanced small disk interface (EDSI), Integrated DriveElectronics (IDE), Firewire, universal flash storage (UFS), WIFI andBluetooth. Thus, the memory system and the data processing system inaccordance with the present embodiment may be applied to wired/wirelesselectronic devices or particularly mobile electronic devices.

The memory device 6030 may be implemented by a nonvolatile memory. Forexample, the memory device 6030 may be implemented by variousnonvolatile memory devices such as an erasable and programmable ROM(EPROM), an electrically erasable and programmable ROM (EEPROM), a NANDflash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistiveRAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfermagnetic RAM (STT-RAM).

The memory controller 6020 and the memory device 6030 may be integratedinto a single semiconductor device. For example, the memory controller6020 and the memory device 6030 may construct a solid state driver (SSD)by being integrated into a single semiconductor device. The memory card6000 may be a PC card (PCMCIA: Personal Computer Memory CardInternational Association), a compact flash (CF) card, a smart mediacard (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC,RS-MMC, MMCmicro and eMMC), an SD card (e.g., SD, miniSD, microSD andSDHC) and a universal flash storage (UFS),

FIG. 11 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance withthe present embodiment.

Referring to FIG. 11, the data processing system 6200 may include amemory device 6230 having one or more nonvolatile memories and a memorycontroller 6220 for controlling the memory device 6230. The dataprocessing system 6200 illustrated in FIG. 11 may serve as a storagemedium such as a memory card (CF, SD, micro-SD or the like) or USBdevice, as described with reference to FIG. 1. The memory device 6230may correspond to the memory device 150 in the memory system 110illustrated in FIG. 1, and the memory controller 6220 may correspond tothe controller 130 in the memory system 110 illustrated in FIG. 1.

The memory controller 6220 may control a read, write or erase operationon the memory device 6230 in response to a request of the host 6210, andthe memory controller 6220 may include one or more CPUs 6221, a buffermemory such as RAM 6222, an ECC circuit 6223, a host interface 6224 anda memory interface such as an NVM interface 6225.

The CPU 6221 may control overall operations on the memory device 6230,for example, read, write, file system management and bad page managementoperations. The RAM 6222 may be operated according to control of the CPU6221, and used as a work memory, buffer memory or cache memory. When theRAM 6222 is used as a work memory, data processed by the CPU 6221 may betemporarily stored in the RAM 6222. When the RAM 6222 is used as abuffer memory, the RAM 6222 may be used for buffering data transmittedto the memory device 6230 from the host 6210 or transmitted to the host6210 from the memory device 6230. When the RAM 6222 is used as a cachememory, the RAM 6222 may assist the low-speed memory device 6230 tooperate at high speed.

The ECC circuit 6223 may correspond to the ECC unit 138 of thecontroller 130 illustrated in FIG. 1. As described with reference toFIG. 1, the ECC circuit 6223 may generate an ECC (Error Correction Code)for correcting a fail bit or error bit of data provided from the memorydevice 6230. The ECC circuit 6223 may perform error correction encodingon data provided to the memory device 6230, thereby forming data with aparity bit. The parity bit may be stored in the memory device 6230. TheECC circuit 6223 may perform error correction decoding on data outputtedfrom the memory device 6230. At this time, the ECC circuit 6223 maycorrect an error using the parity bit. For example, as described withreference to FIG. 1, the ECC circuit 6223 may correct an error using theLDPC code, BCH code, turbo code, Reed-Solomon code, convolution code,RSC or coded modulation such as TCM or BCM.

The memory controller 6220 may transmit/receive data to/from the host6210 through the host interface 6224, and transmit/receive data to/fromthe memory device 6230 through the NVM interface 6225. The hostinterface 6224 may be connected to the host 6210 through a PATA bus,SATA bus, SCSI, USB, PCIe or NAND interface. The memory controller 6220may have a wireless communication function with a mobile communicationprotocol such as WiFi or Long Term Evolution (LTE). The memorycontroller 6220 may be connected to an external device, for example, thehost 6210 or another external device, and then transmit/receive datato/from the external device. In particular, as the memory controller6220 is configured to communicate with the external device through oneor more of various communication protocols, the memory system and thedata processing system in accordance with the present embodiment may beapplied to wired/wireless electronic devices or particularly a mobileelectronic device.

FIG. 12 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance withthe present embodiment. FIG. 12 schematically illustrates an SSD towhich the memory system in accordance with the present embodiment isapplied.

Referring to FIG. 12, the SSD 6300 may include a controller 6320 and amemory device 6340 including a plurality of nonvolatile memories. Thecontroller 6320 may correspond to the controller 130 in the memorysystem 110 of FIG. 1, and the memory device 6340 may correspond to thememory device 150 in the memory system of FIG. 1.

More specifically, the controller 6320 may be connected to the memorydevice 6340 through a plurality of channels CH1 to CHi. The controller6320 may include one or more processors 6321, a buffer memory 6325, anECC circuit 6322, a host interface 6324 and a memory interface, forexample, a nonvolatile memory interface 6326.

The buffer memory 6325 may temporarily store data provided from the host6310 or data provided from a plurality of flash memories NVM included inthe memory device 6340, or temporarily store meta data of the pluralityof flash memories NVM, for example, map data including a mapping table.The buffer memory 6325 may be embodied by volatile memories such asDRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM or nonvolatile memoriessuch as FRAM, ReRAM, STT-MRAM and PRAM. For convenience of description,FIG. 12 illustrates that the buffer memory 6325 exists in the controller6320. However, the buffer memory 6325 may exist outside the controller6320.

The ECC circuit 6322 may calculate an ECC value of data to be programmedto the memory device 6340 during a program operation, perform an errorcorrection operation on data read from the memory device 6340 based onthe ECC value during a read operation, and perform an error correctionoperation on data recovered from the memory device 6340 during a faileddata recovery operation.

The host interface 6324 may provide an interface function with anexternal device, for example, the host 6310, and the nonvolatile memoryinterface 6326 may provide an interface function with the memory device6340 connected through the plurality of channels.

Furthermore, a plurality of SSDs 6300 to which the memory system 110 ofFIG. 1 is applied may be provided to embody a data processing system,for example, RAID (Redundant Array of Independent Disks) system. At thistime, the RAID system may include the plurality of SSDs 6300 and a RAIDcontroller for controlling the plurality of SSDs 6300. When the RAIDcontroller performs a program operation in response to a write commandprovided from the host 6310, the RAID controller may select one or morememory systems or SSDs 6300 according to a plurality of RAID levels,that is, RAID level information of the write command provided from thehost 6310 in the SSDs 6300, and output data corresponding to the writecommand to the selected SSDs 6300. Furthermore, when the RAID controllerperforms a read command in response to a read command provided from thehost 6310, the RAID controller may select one or more memory systems orSSDs 6300 according to a plurality of RAID levels, that is, RAID levelinformation of the read command provided from the host 6310 in the SSDs6300, and provide data read from the selected SSDs 6300 to the host6310.

FIG. 13 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance withthe present embodiment. FIG. 13 schematically illustrates an embeddedMulti-Media Card (eMMC) to which the memory system in accordance withthe present embodiment is applied.

Referring to FIG. 13, the eMMC 6400 may include a controller 6430 and amemory device 6440 embodied by one or more NAND flash memories. Thecontroller 6430 may correspond to the controller 130 in the memorysystem 110 of FIG. 1, and the memory device 6440 may correspond to thememory device 150 in the memory system 110 of FIG. 1.

More specifically, the controller 6430 may be connected to the memorydevice 6440 through a plurality of channels. The controller 6430 mayinclude one or more cores 6432, a host interface 6431 and a memoryinterface, for example, a NAND interface 6433.

The core 6432 may control overall operations of the eMMC 6400, the hostinterface 6431 may provide an interface function between the controller6430 and the host 6410, and the NAND interface 6433 may provide aninterface function between the memory device 6440 and the controller6430. For example, the host interface 6431 may serve as a parallelinterface, for example, MMC interface as described with reference toFIG. 1. Furthermore, the host interface 6431 may serve as a serialinterface, for example, UHS ((Ultra High Speed)-I/UHS-II) interface.

FIGS. 14 to 17 are diagrams schematically illustrating other examples ofthe data processing system including the memory system in accordancewith the present embodiment. FIGS. 14 to 17 schematically illustrate UFS(Universal Flash Storage) systems to which the memory system inaccordance with the present embodiment is applied.

Referring to FIGS. 14 to 17, the UFS systems 6500, 6600, 6700 and 6800may include hosts 6510, 6610, 6710 and 6810, UFS devices 6520, 6620,6720 and 6820 and UFS cards 6530, 6630, 6730 and 6830, respectively. Thehosts 6510, 6610, 6710 and 6810 may serve as application processors ofwired/wireless electronic devices or particularly mobile electronicdevices, the UFS devices 6520, 6620, 6720 and 6820 may serve as embeddedUFS devices, and the UFS cards 6530, 6630, 6730 and 6830 may serve asexternal embedded UFS devices or removable UFS cards.

The hosts 6510, 6610, 6710 and 6810, the UFS devices 6520, 6620, 6720and 6820 and the UFS cards 6530, 6630, 6730 and 6830 in the respectiveUFS systems 6500, 6600, 6700 and 6800 may communicate with externaldevices, for example, wired/wireless electronic devices or particularlymobile electronic devices through UFS protocols, and the UFS devices6520, 6620, 6720 and 6820 and the UFS cards 6530, 6630, 6730 and 6830may be embodied by the memory system 110 illustrated in FIG. 1. Forexample, in the UFS systems 6500, 6600, 6700 and 6800, the UFS devices6520, 6620, 6720 and 6820 may be embodied in the form of the dataprocessing system 6200, the SSD 6300 or the eMMC 6400 described withreference to FIGS. 11 to 13, and the UFS cards 6530, 6630, 6730 and 6830may be embodied in the form of the memory card 6100 described withreference to FIG. 10.

Furthermore, in the UFS systems 6500, 6600, 6700 and 6800, the hosts6510, 6610, 6710 and 6810, the UFS devices 6520, 6620, 6720 and 6820 andthe UFS cards 6530, 6630, 6730 and 6830 may communicate with each otherthrough an UFS interface, for example, MIPI M-PHY and MIPI UniPro(Unified Protocol) in MIPI (Mobile Industry Processor Interface).Furthermore, the UFS devices 6520, 6620, 6720 and 6820 and the UFS cards6530, 6630, 6730 and 6830 may communicate with each other throughvarious protocols other than the UFS protocol, for example, UFDs, MMC,SD, mini-SD, and micro-SD.

In the UFS system 6500 illustrated in FIG. 14, each of the host 6510,the UFS device 6520 and the UFS card 6530 may include UniPro. The host6510 may perform a switching operation in order to communicate with theUFS device 6520 and the UFS card 6530. In particular, the host 6510 maycommunicate with the UFS device 6520 or the UFS card 6530 through linklayer switching, for example, L3 switching at the UniPro. At this time,the UFS device 6520 and the UFS card 6530 may communicate with eachother through link layer switching at the UniPro of the host 6510. Inthe present embodiment, the configuration in which one UFS device 6520and one UFS card 6530 are connected to the host 6510 has beenexemplified for convenience of description. However, a plurality of UFSdevices and UFS cards may be connected in parallel or in the form of astar to the host 6410, and a plurality of UFS cards may be connected inparallel or in the form of a star to the UFS device 6520 or connected inseries or in the form of a chain to the UFS device 6520.

In the UFS system 6600 illustrated in FIG. 15, each of the host 6610,the UFS device 6620 and the UFS card 6630 may include UniPro, and thehost 6610 may communicate with the UFS device 6620 or the UFS card 6630through a switching module 6640 performing a switching operation, forexample, through the switching module 6640 which performs link layerswitching at the UniPro, for example, L3 switching. The UFS device 6620and the UFS card 6630 may communicate with each other through link layerswitching of the switching module 6640 at UniPro. In the presentembodiment, the configuration in which one UFS device 6620 and one UFScard 6630 are connected to the switching module 6640 has beenexemplified for convenience of description. However, a plurality of UFSdevices and UFS cards may be connected in parallel or in the form of astar to the switching module 6640, and a plurality of UFS cards may beconnected in series or in the form of a chain to the UFS device 6620.

In the UFS system 6700 illustrated in FIG. 16, each of the host 6710,the UFS device 6720 and the UFS card 6730 may include UniPro, and thehost 6710 may communicate with the UFS device 6720 or the UFS card 6730through a switching module 6740 performing a switching operation, forexample, through the switching module 6740 which performs link layerswitching at the UniPro, for example, L3 switching. At this time, theUFS device 6720 and the UFS card 6730 may communicate with each otherthrough link layer switching of the switching module 6740 at the UniPro,and the switching module 6740 may be integrated as one module with theUFS device 6720 inside or outside the UFS device 6720. In the presentembodiment, the configuration in which one UFS device 6720 and one UFScard 6730 are connected to the switching module 6740 has beenexemplified for convenience of description. However, a plurality ofmodules each including the switching module 6740 and the UFS device 6720may be connected in parallel or in the form of a star to the host 6710or connected in series or in the form of a chain to each other.Furthermore, a plurality of UFS cards may be connected in parallel or inthe form of a star to the UFS device 6720.

In the UFS system 6800 illustrated in FIG. 17, each of the host 6810,the UFS device 6820 and the UFS card 6830 may include M-PHY and UniPro.The UFS device 6820 may perform a switching operation in order tocommunicate with the host 6810 and the UFS card 6830. In particular, theUFS device 6820 may communicate with the host 6810 or the UFS card 6830through a switching operation between the M-PHY and UniPro module forcommunication with the host 6810 and the M-PHY and UniPro module forcommunication with the UFS card 6830, for example, through a target ID(Identifier) switching operation. At this time, the host 6810 and theUFS card 6830 may communicate with each other through target IDswitching between the M-PHY and UniPro modules of the UFS device 6820.In the present embodiment, the configuration in which one UFS device6820 is connected to the host 6810 and one UFS card 6830 is connected tothe UFS device 6820 has been exemplified for convenience of description.However, a plurality of UFS devices may be connected in parallel or inthe form of a star to the host 6810, or connected in series or in theform of a chain to the host 6810, and a plurality of UFS cards may beconnected in parallel or in the form of a star to the UFS device 6820,or connected in series or in the form of a chain to the UFS device 6820.

FIG. 18 is a diagram schematically illustrating another example of thedata processing system including the memory system in accordance with anembodiment. FIG. 18 is a diagram schematically illustrating a usersystem to which the memory system in accordance with the presentembodiment is applied.

Referring to FIG. 18, the user system 6900 may include an applicationprocessor 6930, a memory module 6920, a network module 6940, a storagemodule 6950 and a user interface 6910.

More specifically, the application processor 6930 may drive componentsincluded in the user system 6900, for example, an OS, and includecontrollers, interfaces and a graphic engine which control thecomponents included in the user system 6900. The application processor6930 may be provided as System-on-Chip (SoC).

The memory module 6920 may be used as a main memory, work memory, buffermemory or cache memory of the user system 6900. The memory module 6920may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM,DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatileRAM such as PRAM, ReRAM, MRAM or FRAM. For example, the applicationprocessor 6930 and the memory module 6920 may be packaged and mounted,based on POP (Package on Package).

The network module 6940 may communicate with external devices. Forexample, the network module 6940 may not only support wiredcommunication, but also support various wireless communication protocolssuch as code division multiple access (CDMA), global system for mobilecommunication (GSM), wideband CDMA (WCDMA), CDMA-2000, time divisionmultiple access (TDMA), long term evolution (LTE), worldwideinteroperability for microwave access (Wimax), wireless local areanetwork (WLAN), ultra-wideband (UWB), Bluetooth, wireless display(WI-DI), thereby communicating with wired/wireless electronic devices orparticularly mobile electronic devices. Therefore, the memory system andthe data processing system, in accordance with an embodiment of thepresent invention, can be applied to wired/wireless electronic devices.The network module 6940 may be included in the application processor6930.

The storage module 6950 may store data, for example, data received fromthe application processor 6930, and then may transmit the stored data tothe application processor 6930. The storage module 6950 may be embodiedby a nonvolatile semiconductor memory device such as a phase-change RAM(PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash,NOR flash and 3D NAND flash, and provided as a removable storage mediumsuch as a memory card or external drive of the user system 6900. Thestorage module 6950 may correspond to the memory system 110 describedwith reference to FIG. 1. Furthermore, the storage module 6950 may beembodied as an SSD, eMMC and UFS as described above with reference toFIGS. 12 to 17.

The user interface 6910 may include interfaces for inputting data orcommands to the application processor 6930 or outputting data to anexternal device. For example, the user interface 6910 may include userinput interfaces such as a keyboard, a keypad, a button, a touch panel,a touch screen, a touch pad, a touch ball, a camera, a microphone, agyroscope sensor, a vibration sensor and a piezoelectric element, anduser output interfaces such as a liquid crystal display (LCD), anorganic light emitting diode (OLED) display device, an active matrixOLED (AMOLED) display device, an LED, a speaker and a motor.

Furthermore, when the memory system 110 of FIG. 1 is applied to a mobileelectronic device of the user system 6900, the application processor6930 may control overall operations of the mobile electronic device, andthe network module 6940 may serve as a communication module forcontrolling wired/wireless communication with an external device. Theuser interface 6910 may display data processed by the processor 6930 ona display/touch module of the mobile electronic device, or support afunction of receiving data from the touch panel.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

What is claimed is:
 1. A memory system comprising: a memory deviceincluding first and second groups including a plurality of memoryblocks, respectively; and a controller configured to copy data stored inthe first group into the second group, wherein the controller isconfigured to: sort the data read from the first group according tological addresses; and program the sorted data into the second group. 2.The memory system according to claim 1, wherein the controller furthercomprises a memory storing the data read from the first group, andwherein the controller is configured to sort the data stored in thememory.
 3. The memory system according to claim 1, wherein thecontroller is configured to sort the data in an ascending order of thelogical addresses.
 4. The memory system according to claim 2, whereinthe controller is configured to sort the data when a size of the datastored in the memory is equal to or greater than a threshold value. 5.The memory system according to claim 2, wherein the controller isconfigured to program the data into the second group in an interleavingmanner when the data stored in the memory are sorted.
 6. The memorysystem according to claim 1, wherein the data read from the first groupare sequential.
 7. A memory system comprising: a memory device includingfirst and second groups including a plurality of memory blocks,respectively; and a controller configured to issue instructions to eachof a plurality of processor cores, wherein each of the processor coresis configured to exclusively perform assigned operation in response tothe respective instructions during a garbage collection operation, andwherein the controller includes: a first processor core configured tosort data read from the first group based on logical addresses; and asecond processor core configured to program the sorted data into thesecond group.
 8. The memory system according to claim 7, wherein thefirst processor core is configured to sort the data in an ascendingorder of the logical addresses.
 9. The memory system according to claim7, wherein the first processor core is configured to sort the data whena size of the read data is equal to or greater than a threshold value.10. The memory system according to claim 7, wherein the controllerfurther includes a third processor configured to read the data from thefirst group, and wherein the read data are valid.
 11. A memory systemcomprising: a memory device including first and second groups includinga plurality of memory blocks, respectively; and a controller configuredto perform a garbage collection operation of copying data from the firstgroup into the second group, wherein the controller is configured to:sort the data read from the first group if a size of the read datasatisfies a predetermined condition; and program the sorted data intothe second group.
 12. The memory system according to claim 11, whereinthe predetermined condition is satisfied when the size of the read datais equal to or greater than a threshold value.
 13. The memory systemaccording to claim 12, wherein the threshold value is equal to orgreater than units of a page.
 14. The memory system according to claim12, wherein the controller is configured to sort the data according tological addresses.
 15. A memory system comprising: a memory deviceincluding first and second groups including a plurality of memoryblocks, respectively; and a controller configured to copy data from thefirst group into the second group during a garbage collection operation;wherein the controller is configured to: sort the data read from thefirst group if a characteristic of the read data satisfies apredetermined condition; and program the sorted data into the secondgroup.
 16. The memory system according to claim 15, wherein thecontroller is further configured to read meta data corresponding to thedata read from the first group.
 17. The memory system according to claim16, wherein the meta data includes an information of the characteristicof the corresponding data.
 18. The memory system according to claim 15,wherein the predetermined condition is satisfied if the read data arehot.
 19. The memory system according to claim 18, wherein the controlleris configured to sort the data when a size of the read data is equal toor greater than a threshold value.
 20. The memory system according toclaim 15, wherein the controller is configured to sort the data in anascending order of logical addresses.